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FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing ?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 september 2012 FOD8316 2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing features high noise immunity characterized by common mode rejection ? 35kv/? minimum common mode rejection (vcm = 1500vpk) 2.5a peak output current driving capability for most 1200v/150a igbt optically isolated fault sensing feedback ?oft?igbt turn-off built-in igbt protection ? desaturation detection ? under voltage lockout protection 1,414v (peak) working voltage rating 8,000v (peak) transient isolation voltage rating wide supply voltage range from 15v to 30v ? use of p-channel mosfets at output stage enables output voltage swing close to the supply rail (rail-to-rail output) 3.3v/5v, cmos/ttl compatible inputs high speed ? 500ns max. propagation delay over full operating temperature range extended industrial temperate range, -40? to 100? temperature range safety and regulatory ? ul1577, 4,243 v rms for 1 min. ? din en/iec 60747-5-5 r ds(on) of 1 (typ.) offers lower power dissipation user configurable: inverting, non-inverting, auto-reset, auto-shutdown 8mm creepage and clearance distances applications industrial inverter induction heating isolated igbt drive description the FOD8316 is an advanced 2.5a output current igbt drive optocoupler, capable of driving most 1200v/ 150a igbts. it is ideally suited for fast switching driving of power igbts and mosfets used in motor control inverter applications and high performance power systems. it offers critical protection features necessary for preventing fault conditions that lead to destructive thermal runaway of igbts. it utilizes fairchild? patented coplanar packaging technology, optoplanar , and optimized ic design to achieve high noise immunity, characterized by high common mode rejection and power supply rejection specifications. it consists of an integrated gate drive optocoupler featur- ing low r ds(on) cmos transistors to drive the igbt from rail to rail and an integrated high speed isolated feed- back for fault sensing. the device is housed in a com- pact 16-pin small outline plastic package which meets the 8mm creepage and clearance requirements. www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 2 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing truth table pin definitions v in+ v in uvlo (v dd2 ?v e ) desat detected? f a ul t v o x x active x x low xxxyeslowlow lowxxxxlow x high x x x low high low not active no high high pin # name description 1v in+ non inverting gate drive control input 2v in inverting gate drive control input 3v dd1 positive input supply voltage (3v to 5.5v) 4 gnd1 input ground 5 reset fault reset input 6f a ul t fault output (open drain) 7v led1+ led 1 anode (must be left unconnected) 8v led1- led 1 cathode (must be connected to ground) 9v ss output supply voltage (negative) 10 v ss output supply voltage (negative) 11 v o gate drive output voltage 12 v s source of pull-up pmos transistor 13 v dd2 positive output supply voltage 14 desat desaturation voltage input 15 v led2+ led 2 anode (must be left unconnected) 16 v e output supply voltage/igbt emitter 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 3 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing block diagram driver v dd1 v dd2 v led1+ 3 13 7 v s 12 v o 11 v ss 9,10 desat 14 v e 16 v in+ 1 v in? 2 reset fault uvlo desat led1 led2 fault sense optocoupler gate drive optocoupler shield shield 5 fault input ic output ic v led2+ 6 15 gnd1 4 v led1? 8 www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 4 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing safety and insulation ratings as per din en/iec 60747-5-5. this optocoupler is suitable for ?afe electrical insulation?only within the safety limit data. compliance with the safety ratings shall be ensured by means of protective circuits. symbol parameter min. typ. max. unit installation classi?ations per din vde 0110/1.89 table 1 for rated mains voltage < 150vrms i?v for rated mains voltage < 300vrms i?v for rated mains voltage < 450vrms i?v for rated mains voltage < 600vrms i?v for rated mains voltage < 1000vrms i?ii climatic classi?ation 40/100/21 pollution degree (din vde 0110/1.89) 2 cti comparative tracking index 175 v pr input to output test voltage, method b, v iorm x 1.875 = v pr , 100% production test with tm = 1 sec., partial discharge < 5pc 2651 v peak input to output test voltage, method a, v iorm x 1.5 = v pr , type and sample test with tm = 60 sec.,partial discharge < 5 pc 2121 v peak v iorm max working insulation voltage 1,414 v peak v iotm highest allowable over voltage 8000 v peak external creepage 8 mm external clearance 8 mm insulation thickness 0.5 mm safety limit values ?maximum values allowed in the event of a failure t case case temperature 150 ? p s,input input power 100 mw p s,output output power 600 mw r io insulation resistance at t s , v io = 500v 10 9 www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 5 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing absolute maximum ratings (t a = 25? unless otherwise speci?d) stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. notes: 1. maximum pulse width = 10?, maximum duty cycle = 0.2%. 2. this negative output supply voltage is optional. it? only needed when negative gate drive is implemented. refer to ?ual supply operation ?negative bias at vss?on page 23. 3. no derating required across temperature range. 4. derate linearly above 64?, free air temperature at a rate of 10.2mw/? 5. functional operation under these conditions is not implied. permanent damage may occur if the device is subjected to conditions outside these ratings. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. note: 6. during power up or down, it is important to ensure that vin+ remains low until both the input and output supply voltages reaches the proper recommended operating voltages to avoid any momentary instability at the output state. see also the discussion in the ?ime to good power?section on page 23. symbol parameter value units t stg storage temperature -40 to +125 ? t opr operating temperature -40 to +100 ? t j junction temperature -40 to +125 ? t sol lead wave solder temperature (no solder immersion) refer to page 27 for re?w temperature pro?e. 260 for 10 sec ? i f a ul t fault output current 15 ma i o(peak) peak output current (1) 3a v e ?v ss negative output supply voltage (2) 0 to 15 v v dd2 ?v e positive output supply voltage -0.5 to 35 ?(v e ?v ss )v v o(peak) gate drive output voltage -0.5 to 35 v v dd2 ?v ss output supply voltage -0.5 to 35 v v dd1 positive input supply voltage -0.5 to 6 v v in+ , v in- and v reset input voltages -0.5 to v dd1 v v fault fault pin voltage -0.5 to v dd1 v v s source of pull-up pmos transistor voltage v ss + 6.5 to v dd2 v v desat desat voltage v e to v e + 11 v pd i input power dissipation (3)(5) 100 mw pd o output power dissipation (4)(5) 600 mw symbol parameter min. max. unit t a ambient operating temperature -40 +100 ? v dd1 input supply voltage (6) 3 5.5 v v dd2 v ss total output supply voltage 15 30 v v e v ss negative output supply voltage 0 15 v v dd2 v e positive output supply voltage (6) 15 30 ?(v e v ss )v v s source of pull-up pmos transistor voltage v ss + 7.5 v dd2 v www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 6 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing isolation characteristics apply over all recommended conditions, typical value is measured at t a = 25? notes: 7. device is considered a two terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together. 8. 4,243 vrms for 1 minute duration is equivalent to 5,091 vrms for 1 second duration. 9. the input-output isolation voltage is a dielectric voltage rating as per ul1577. it should not be regarded as an input-output continuous voltage rating. for the continuous working voltage rating refer to your equipment level safety specification or din en/iec 60747-5-5 safety and insulation ratings table. electrical characteristics apply over all recommended conditions, typical value is measured at v dd1 = 5v, v dd2 ? v ss = 30v, v e ? v ss = 0v, t a = 25c unless otherwise speci?ed. symbol parameter conditions min. typ. max. units v iso input-output isolation voltage t a = 25?, r.h.< 50%, t = 1.0min, i i-o 10?, 50hz (7)(8)(9) 4,243 v rms r iso isolation resistance v i-o = 500v (7) 10 11 c iso isolation capacitance v i-o = 0v, freq = 1.0mhz (7) 1pf symbol parameter conditions min. typ. max. units figure v in+l , v in-l , v resetl logic low input voltages 0.8 v v in+h , v in-h , v reseth logic high input voltages 2.0 v i in+l , i in-l , i resetl logic low input currents v in = 0.4v -0.5 -0.001 ma i f a ul tl f a ul t logic low output current v fault = 0.4v 5.0 12.0 ma 1, 32 i f a ul th f a ul t logic high output current v fault = v dd1 -40 0.002 ? 32 i oh high level output current v o = v dd2 ?3v -1 -3 a 2, 7, 33 v o = v dd2 ?6v (10) -2.5 a i ol low level output current v o = v ss + 3v 1 3 a 3, 34 v o = v ss + 6v (11) 2.5 a i olf low level output current during fault condition v o ?v ss = 14v 90 185 230 ma 4, 38 v oh high level output voltage i o = ?00ma (12)(13)(14) v s ?1.0v v s ?0.5v v 5, 7, 35 v ol low level output voltage i o = 100ma 0.1 0.5 v 6, 8, 35 i dd1h high level supply current v in+ = v dd1 = 5.5v, v in? = 0v 14 17 ma 9, 36 i dd1l low level supply current v in+ = v in- = 0v, v dd1 = 5.5v 23ma i dd2h high level output supply current v o = open (14) 1 3 ma 10, 11, 37 i dd2l low level output supply current v o = open 0.8 2.8 ma i sh high level source current i o = 0ma 0.65 1.5 ma 37 i sl low level source current i o = 0ma 0.6 1.4 ma 37 i el v e low level supply current -0.5 -0.2 ma 13, 37 i eh v e high level supply current -0.5 -0.25 ma i chg blanking capacitor charge current v desat = 2v (14)(15) -0.13 -0.25 -0.37 ma 12, 38 i dschg blanking capacitor discharge current v desat = 7v 10 36 ma 38 www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 7 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing notes: 10. maximum pulse width = 10?, maximum duty cycle = 0.2%. 11. maximum pulse width = 4.99ms, maximum duty cycle = 99.8%. 12. v oh is measured with the dc load current in this testing (maximum pulse width = 1ms, maximum duty cycle = 20%).when driving capacitive loads, v oh will approach v dd as i oh approaches zero units. 13. positive output supply voltage (v dd2 ?v e ) should be at least 15v. this is to ensure adequate margin in excess of the maximum under voltage lockout threshold v uvlo+ of 13.5v. 14. when v dd2 ?v e > v uvlo and output state v o of the FOD8316 is allowed to go high, the desat detection feature will be active and will provide the primary source of igbt protection. uvlo is needed to ensure desat detection is functional. 15. the blanking time, t blank is adjustable by an external capacitor (c blank ) where t blank = c blank * (v desat /i chg ) switching characteristics apply over all recommended conditions, typical value is measured at v dd1 = 5v, v dd2 ? v ss = 30v, v e ? v ss = 0v, t a = 25c unless otherwise speci?ed. v uvlo+ under voltage lockout threshold (14) v o > 5v @ 25? 11.5 13.5 v 15, 29, 39 v uvlo- v o < 5v @ 25? 9 10 v uvlo hys under voltage lockout threshold hysteresis @ 25? 0.4 1.5 v v desat desat threshold (14) v dd2 ?v e > v ulvo- , v o < 5v 6.0 7.0 9.0 v 16, 38 symbol parameter conditions min. typ. max. units figure t phl propagation delay time to logic low output (17) rg = 10 , cg = 10nf, f = 10khz, duty cycle = 50% (16) 300 500 ns 17, 18, 19, 20, 21, 22, 40, 48 t plh propagation delay time to logic high output (18) 250 500 ns pwd pulse width distortion, | t phl ?t plh | (19) 50 300 ns pdd skew propagation delay difference between any two parts or channels, ( t phl ?t plh ) (20) ?50 350 ns t r output rise time (10% ?90%) 34 ns 40, 48 t f output fall time (90% ?10%) 34 ns t desat(90%) desat sense to 90% v o delay (21) rg = 10 , cg = 10nf, v dd2 ?v ss = 30v 850 ns 23, 41 t desat(10%) desat sense to 10% v o delay (21) 2 3 ? 24, 26, 27, 41 t desat(f a ul t ) desat sense to low level f a ul t signal delay (22) 1.8 5 s 25, 41, 49 t desat(low) desat sense to desat low propagation delay (23) 850 ns 41 t reset (f a ul t ) reset to high level f a ul t signal delay (24) 3 6 20 ? 28, 42, 49 pw reset reset signal pulse width 1.2 ? t uvlo on uvlo turn on delay (25) v dd2 = 20v in 1.0ms ramp 4 s 29, 43 t uvlo off uvlo turn off delay (26) 3s symbol parameter conditions min. typ. max. units figure electrical characteristics (continued) apply over all recommended conditions, typical value is measured at v dd1 = 5v, v dd2 ? v ss = 30v, v e ? v ss = 0v, t a = 25c unless otherwise speci?ed. www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 8 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing notes: 16. this load condition approximates the gate load of a 1200 v/150a igbt. 17. t phl propagation delay is measured from the 50% level on the falling edge of the input pulse(v in+ , v in- ) to the 50% level of the falling edge of the v o signal. refer to figure 48. 18. t phl propagation delay is measured from the 50% level on the rising edge of the input pulse (v in+ , v in- ) to the 50% level of the rising edge of the v o signal. refer to figure 48. 19. pwd is defined as | t phl ?t plh | for any given device. 20. the difference between t phl and t plh between any two FOD8316 parts under same operating conditions, with equal loads. 21. this is the amount of time the desat threshold must be exceeded before v o begins to go low. this is supply voltage dependent. see figure 49. 22. this is the amount of time from when the desat threshold is exceeded, until the fault output goes low. see figure 49. 23. this is the amount of time the desat threshold must be exceeded before v o begins to go low, and the fault output to go low. see figure 49. 24. this is the amount of time from when reset is asserted low, until fault output goes high. see figure 49. 25. t uvlo on uvlo turn on delay is measured from v uvlo+ threshold voltage of the output supply voltage (v dd2 ) to the 5v level of the rising edge of the v o signal. 26. t uvlo off uvlo turn off delay is measured from v uvlo threshold voltage of the output supply voltage (v dd2 ) to the 5v level of the falling edge of the v o signal. 27. t gp time to good power is measured from 13.5v level of the rising edge of the output supply voltage (v dd2 ) to the 5v level of the rising edge of the v o signal. 28. common mode transient immunity at output high state is the maximum tolerable negative dvcm/dt on the trailing edge of the common mode pulse, v cm , to assure that the output will remain in the high state (i.e., v o > 15 v or fault > 2 v). 29.common mode transient immunity at output low state is the maximum positive tolerable dvcm/dt on the leading edge of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e., v o < 1.0 v or fault < 0.8 v). t gp time to good power (27) v dd2 = 0 to 30v in 10? ramp 30 ? 30, 31, 43 | cm h | common mode transient immunity at output high t a = 25?, v dd1 = 5v, v dd2 = 25v, v ss = ground, v cm = 1500vpk (28) 35 50 kv/? 45, 46 | cm l | common mode transient immunity at output low t a = 25?, v dd1 = 5v, v dd2 = 25v, v ss = ground, v cm = 1500vpk (29) 35 50 kv/? 44, 47 symbol parameter conditions min. typ. max. units figure switching characteristics (continued) apply over all recommended conditions, typical value is measured at v dd1 = 5v, v dd2 ? v ss = 30v, v e ? v ss = 0v, t a = 25c unless otherwise speci?ed. www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 9 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing typical performance characteristics i oh ? output high current (a) figure 2. output high current (i oh ) vs. temperature figure 4. low level output current (i olf ) vs. output voltage (v o ) figure 5. output high voltage (v oh ? dd2 ) vs. temperature figure 3. output low current (i ol ) vs. temperature 7 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v o = v dd2 ? 6v v o = v dd2 ? 3v i ol ? output low current (a) 7 6 5 4 3 2 1 0 (v oh ?v dd2 ) ? high output voltage drop (v) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v o = v ss + 6v v o = v ss + 3v v dd2 ? v ss = 30v v dd1 = 5v i olf ? low level output current during fault conditions (ma) 225 200 175 150 125 100 75 50 25 0 5 10 15 20 25 30 v o ? output voltage (v) -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30v v dd1 = 5v v dd2 ? v ss = 30v v dd1 = 5v i faultl ? fault current (ma) figure 1. fault logic low output current (i faultl ) vs. fault logic low output voltage (v faultl ) 50 40 30 20 10 0 01234 5 v faultl ? fault voltage (v) v dd1 = 5v vin+ = 5v i led2+ = 10ma t a = 25 c t a = -40 c i o = -650 a i o = -100ma t a = 25 c t a = 100 c v dd2 ? v ss = 30v v dd1 = 5v v in+ = 5v v ol ? output low voltage (v) 0.25 0.20 0.15 0.10 0.05 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30v v dd1 = 5v v in+ = 0v i o = 100ma figure 6. output low voltage (v ol ) vs. temperature www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 10 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing typical performance characteristics (continued) figure 7. output high voltage (v oh ) vs. output high current (i oh ) figure 9. supply current (i dd1 ) vs. temperature figure 10. output supply current (i dd2 ) vs. temperature figure 12. blanking capacitor charging current (i chg ) vs. temperature figure 11. output supply current (i dd2 ) vs. output supply voltage (v dd2 ) figure 8. output low voltage (v ol ) vs. output low current (i ol ) v oh ? output high voltage (v) 30 29 28 27 26 25 0 0.5 1.0 1.5 2.0 2.5 i oh ? output high current (a) v dd2 ? v ss = 30v v dd1 = 5v v in+ = 5v i dd1 ? supply current (ma) 20 15 10 5 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd1 = 5.5v v in+ = 5v (i dd1h ) or 0v (i dd1l ) i dd1h i dd1l t a = -40 c 25 c 100 c i dd2 ? output supply current (ma) 1.2 1.0 0.8 0.6 0.4 15 20 25 30 v dd2 ? output supply voltage (v) v ol ? output low voltage (v) 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 2.5 i ol ? output low current (a) v dd2 ? v ss = 30v v dd1 = 5v v in+ = 0v -40 c 25 c t a = 100 c i dd2 ? output supply current (ma) 1.4 1.2 1.0 0.8 0.6 0.4 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30v v dd1 = 5v v in+ = 5v (i dd2h ) or 0v (i dd2l ) i dd2h i dd2l i dd2h i dd2l v dd1 = 5v v in+ = 5v (i dd2h ) or 0v (i dd2l ) i chg ? blanking capacitor charging current (ma) -0.15 -0.20 -0.25 -0.30 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30v v dd1 = 5v v in+ = 5v v desat = 0v to 6v www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 11 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing typical performance characteristics (continued) i s ? source current (ma) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 i o ? output current (ma) v desat ? desat threshold (v) 8.0 7.5 7.0 6.5 6.0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30v v dd1 = 5v v in+ = 5v v dd2 ? v ss = 30v v dd1 = 5v v in+ = 5v -40 c 25 c 100 c t p ? propagation delay ( s) 0.5 0.4 0.3 0.2 0.1 figure 17. propagation delay (t p ) vs. temperature -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30v v dd1 = 5v f = 10khz 50% duty cycle r l = 10 , c l = 10nf t plh t phl t p ? propagation delay ( s) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 figure 18. propagation delay (t p ) vs. supply voltage (v dd2 ) 15 20 25 30 v dd2 ? supply voltage (v) v dd1 = 5v f = 10khz 50% duty cycle r l = 10 , c l = 10nf t plh t phl figure 13. supply current (i e ) vs. temperature figure 16. desat threshold (v desat ) vs. temperature figure 14. source current (i s ) vs. output current (i o ) i e ? supply current (ma) -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30v v dd1 = 5v v in+ = 5v (i eh ) / 0v (i el ) i el i eh figure 15. under voltage lockout threshold (v uvlo ) vs. temperature v uvlo ? under voltage lockout threshold (v) 15 10 5 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd1 = 5v v in+ = 5v v uvlo? v uvlo+ www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 12 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing typical performance characteristics (continued) t p ? propagation delay ( s) t desat(90%) ? desat sense to 90% v o delay ( s) 0.40 0.35 0.30 0.25 0.20 figure 21. propagation delay (t p ) vs. load capacitance (c l ) 0 20406080100 c l ? load capacitance (nf) v dd2 ? v ss = 30v v dd1 = 5v f = 10khz 50% duty cycle r l = 10 t plh t phl t p ? propagation delay ( s) 0.40 0.35 0.30 0.25 0.20 figure 22. propagation delay (t p ) vs. load resistance (r l ) 0 1020304050 r l ? load resistance ( ) v dd2 ? v ss = 30v v dd1 = 5v f = 10khz 50% duty cycle c l = 10nf t plh t phl t plh ? propagation delay ( s) 0.45 0.40 0.35 0.30 0.25 figure 19. propagation delay time to logic high output (t plh ) vs. temperature figure 20. propagation delay time to logic low output (t phl ) vs. temperature -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30v f = 10khz 50% duty cycle r l = 10 , c l = 10nf v dd1 = 4.5v v dd1 = 5.0v v dd1 = 5.5v t phl ? propagation delay ( s) 0.35 0.30 0.25 0.20 0.15 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30v f = 10khz 50% duty cycle r l = 10 , c l = 10nf v dd1 = 4.5v v dd1 = 5.0v v dd1 = 5.5v 1.2 1.1 1.0 0.9 0.8 figure 23. desat sense to 90% v o (t desat(90%) ) vs. temperature figure 24. desat sense to 10% v o delay (t desat(10%) ) vs. temperature -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30v v dd1 = 5v v in+ = 5v r l = 10 , c l = 10nf t desat(10%) ? desat sense to 10% v o delay ( s) 3.0 2.5 2.0 1.5 1.0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 15 or 30v v dd1 = 5v v in+ = 5v r l = 10 , c l = 10nf v dd2 ? v ss = 30v v dd2 ? v ss = 15v www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 13 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing typical performance characteristics (continued) 0.0030 0.0250 0.0020 0.0015 0.0010 10 20 30 40 50 r l ? load resistance ( ) v dd2 ? v ss = 15v or 30v v dd1 = 5v v in+ = 5v c l = 10nf t desat(10%) ? desat sense to 10% v o delay ( s) v dd2 ? v ss = 30v v dd2 ? v ss = 15v t reset(fault) ? reset to high level fault signal delay ( s) 10 9 8 7 6 5 4 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30v v in+ = 5v r l = 10 , c l = 10nf v dd1 = 5.5v v dd1 = 5.0v v dd1 = 4.5v figure 25. desat sense to low fault signal delay (t desat(fault) ) vs. temperature figure 26. desat sense to 10% v o delay (t desat(10%) ) vs. load capacitance (c l ) figure 27. desat sense to 10% v o delay (t desat(10%) ) vs. load resistance (r l ) figure 28. reset to high level fault signal delay (t reset(fault) ) vs. temperature t desat(fault) ? desat sense to low fault signal delay ( s) 2.6 2.4 2.2 2.0 1.8 1.6 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 ? v ss = 30v v dd1 = 5v v in+ = 5v r l = 10 , c l = 10nf v e ? v ss = 0v v e ? v ss = 15v 0.008 0.006 0.004 0.002 0 0 5 10 15 20 25 30 c l ? load capacitance (nf) v dd2 ? v ss = 15v or 30v v dd1 = 5v v in+ = 5v r l = 10 t desat(10%) ? desat sense to 10% v o v dd2 ? v ss = 30v v dd2 ? v ss = 15v figure 29. under voltage lockout threshold delay (t uvlo ) vs. temperature t uvlo ? under voltage lockout threshold delay ( s) 10 8 6 4 2 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 = 20v v dd1 = 5v v in+ = 5v f = 50hz, 50% duty cycle t r = 1ms t uvlo on t uvlo off figure 30. time to good power (t gp ) vs. supply voltage (v dd2 ) t gp ? time to good power ( s) 100 80 60 40 20 0 15 25 20 30 v dd2 ? supply voltage (v) v dd1 = 5v v in+ = 5v f = 50hz, 50% duty cycle www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 14 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing typical performance characteristics (continued) figure 31. time to good power (t gp ) vs. temperature t gp ? time to good power ( s) 120 100 80 60 40 20 0 -40 -20 0 20 40 60 80 100 t a ? temperature ( c) v dd2 = 15v to 30v v dd1 = 5v v in+ = 5v f = 50hz 50% duty cycle www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 15 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing test circuits figure 32. fault output current (i f a ul t l ) and (i f a ul t h ) test circuit figure 33. high level output current (i oh ) test circuit figure 34. low level output current (i ol ) test circuit 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 0.1f 0.1f 10ma 5v + C C + i fault v fault v fault = 0.4v for i faultl v fault = 5.0v for i faulth switch a closed for i faultl switch a opened for i faulth *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). a 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 pulse gen pw = 10s period = 5ms 5v C + 0.1f 0.1f 47f 47f 0.1f 0.1f + C 30v + C v e + C 3k v o + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). pulse gen pw = 4.99ms period = 5ms 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 5v C + 0.1f 0.1f 47f 0.1f + C 30v + C v e + C 3k 47f 0.1f v o + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 16 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing test circuits (continued) figure 35. high level (v oh ) and low level (v ol ) output voltage test circuit figure 36. high level (i dd1h ) and low level (i dd1l ) supply current test circuit figure 37. high level (i dd2h ), low level (i dd2l ) output supply current, high level (i sh ), low level (i sl ) source current, v e high level (i eh ), and v e low level (i el ) supply current test circuit 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 v e v o switch a for v oh test switch b for v ol test 0.1f a a b b 0.1f 0.1f 100ma pulsed 100ma pulsed 3k 5v 30v + C + C + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). switch a for i dd1h test switch b for i dd1l test 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 i dd1 0.1f 5v + C a b *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). switch a for i dd2h, i sh and i eh test switch b for i dd2l, i sl and i el test i dd2 i s i e 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 v e v o 0.1f 0.1f 0.1f 5v 30v + C + C + C a b *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 17 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing test circuits (continued) figure 38. low level output current during fault conditions (i olf ), blanking capacitor charge current (i chg ), blanking capacitor discharging current (i dschg ) and desat threshold (v desat ) test circuit figure 39. under voltage lockout threshold (v uvlo ) test circuit figure 40. propagation delay (t plh , t phl ), pulse width distortion (pwd), rise time (t r ) and fall time (t f ) test circuit 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 v e v desat v o i chg/dschg i olf 0.1f rl 0.1f 10nf 0.1f 3k 5v 30v + C + C + C + C v rl *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 v o 0.1f 0.1f 5v dc sweep 0 to 15v (100 steps) parameter analyzer + C + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 v e v o 0.1f 0.1f 10nf 0.1f 3k rl 5v 30v + C + C + C f = 10khz dc = 50% + C v cl *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 18 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing test circuits (continued) figure 41. desat sense (t desat(90%) , t desat(10%) ), desat fault (t desat(f a ul t ) ), and (t desat(low) ) test circuit figure 42. reset delay (t reset (f a ul t ) ) test circuit figure 43. under voltage lockout delay (t uvlo ) and time to good power (t gp ) test circuit 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 v e v o 0.1f 0.1f 100pf 10nf 0.1f 3k rl 5v 30v + C + C + C low to high + C v fault *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 v e v o 0.1f 0.1f 10nf 0.1f 3k rl 5v 30v + C + C + C v fault strobe 8v + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 v e v o v dd2 ** **1.0ms ramp for t uvlo 10 s ramp for t gp 0.1f 0.1f 0.1f 3k 5v + C + C + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 19 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing test circuits (continued) figure 44. common mode low (cm l ) test circuit @ led1 off figure 45. common mode high (cm h ) test circuit @ led1 on 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 scope v cm floating gnd 0.1f 0.1f 25v 10nf 1k 10 5v 300pf *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 scope v cm floating gnd 0.1f 0.1f 25v 10nf 1k 10 5v 300pf *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 20 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing test circuits (continued) figure 46. common mode high (cm h ) test circuit @ led2 off figure 47. common mode low (cm l ) test circuit @ led2 on 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 v cm floating gnd 0.1f 0.1f 25v 10nf 1k 10 5v 300pf scope *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- * v e v led2+ desat v dd2 v s v o v ss v ss 16 15 14 13 12 11 10 9 FOD8316 v cm floating gnd 0.1f 0.1f 25v 10nf 1k 10 750 5v 300pf scope 9v + C *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 21 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing timing diagrams figure 48. propagation delay (t plh , t phl ), rise time (t r ) and fall time (t f ) timing diagram figure 49. de?itions for fault reset input (reset ), desaturation voltage input (desat), output voltage (v o ) and fault output (f a ul t ) timing waveforms v in+ v in? v o 2.5v 0v t r 90% 50% 10% 2.5v t plh t phl t f reset v desat v o t desat (low) fault t desat (90%) t desat (10%) t desat (fault) t reset (fault) 50% 90% 7v 10% 50% 50% (0.5 x v dd1 ) www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 22 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing application information figure 50. recommended application circuit functional description the typical application circuit is shown in figure 50 and the functional behavioral of the FOD8316 is illustrated by the detailed internal schematic shown in figure 51. this helps explain the interaction and sequence of internal and external signals, together with the timing diagrams. 1. non-inverting and inverting inputs there are two cmos/ttl compatible inputs, v in+ and v in- to control the igbt, in non-inverting and inverting configurations respectively. when v in- is set to low, v in+ controls the driver output, v o , in non-inverting configura- tion. when v in+ is set to high, v in- controls the driver output in inverting configuration. the relationship between the inputs and output are illustrated in the figure 52. during normal operation, when no fault is detected, the fault output, which is an open-drain configuration, will be latched to high state. this allows the gate driver to be controlled by the input logic signal. when a fault is detected, the fault output will be latched to low state. this condition will remain until the reset pin is also pulled low for a period longer than pw reset . while setting the reset pin to a low state, the input pins must be pulled to low to ensure an output state (v in+ is low or v in- is high). *pin 8 (v led1- ) is internally connected to pin 4 (gnd1). 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 + +? ? + ? v in+ v in? v dd1 gnd1 reset fault v led1+ v led1- v e v led2+ desat v dd2 v s v o v ss v ss FOD8316 micro controller 1k 330pf + C 0.1f 5v 3-phase output + C + C c2 1f c1 1f d1 c3 10f 100pf 100 v dd2 = 15v d desat rg v f v ss = ?8v v ce v ce q1 q2 figure 51. detailed internal schematic v dd2 13 v s 12 v o 11 50x 1x v ss 9,10 desat + ? ? + 14 250 a 12v v e 16 v in+ 1 15 7 v dd1 3 v in? 2 v led1? v led+ v led2+ 8 gnd1 5 s pulse generator gate drive optocoupler fault sense optocoupler uvlo comparator delay q rs 4 reset 5 fault 6 v desat www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 23 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing 2. gate driver output a pair of pmos and nmos transistors made up the output driver stage, which facilitates close to rail-to-rail output swing. this feature allows a tight control of gate voltage during on-state and short circuit condition. the output driver is typically capable of sinking 2a and sourc- ing 2a at room temperature. due to the low rds (on) of the mosfets, the power dissipation is reduced as compared to those bipolar-type driver output stages. the absolute maximum rating of the output peak current, i o(peak) is 3a, thus the careful selection of the gate resistor, rg, is required to limit the short circuit current of the igbt. as shown in figure 51, the gate driver output is influ- enced by signals from the photodetector circuitry, the uvlo comparator and the desat signals. under no fault condition, normal operation resumes while the sup- ply voltage is above the uvlo threshold, the output of the photodetector will drive the mosfets of the output stage. the logic circuitry of the output stage will ensure that the push-pull devices will never be turned ?n?simulta- neously. when the output of the photodetector is high, the output, v o will be pulled to high state by turning on the pmos. when the output of the photodetector is low, v o will be pulled to low state by turning on the nmos. when v dd2 supply goes below v uvlo , which is the des- ignated ulvo threshold at the comparator, v o will be pulled down to low state regardless of photodetector output. when desaturation is detected, v o will turn off slowly as it is pulled low by the nmos 1x device, the input to the fault sense circuitry will be latched to high state and turns on the led. when v o goes below 2v, the nmos 50x device turns on again, clamping the igbt gate firmly to v ss . the fault sense signal will remain latched in the high state until the led of the gate driver circuitry turns off. 3. desaturation protection, fault output desaturation detection protection ensures the protection of the igbt at short circuit by monitoring the collector- emitter voltage of the igbt in the half bridge. when the desat voltage goes up and reaches above the threshold voltage, a short circuit condition is detected and the driver output stage will execute a ?oft?igbt turn-off and will be eventually driven low. this sequence is illustrated in figure 53. the fault open-drain output is triggered active low to report a desaturation error. it could only be cleared by activating active low by the external controller to the reset input. the desat fault detector should be disabled for a short time period (blanking time) before the igbt turns on to allow the collector voltage to fall below desat thresh- old. this blanking period protects against false trigger of the desat while the igbt is turning on. 4. ?oft?turn-off the soft turn-off feature ensures the safe turn off of the igbt under fault condition. this reduces the voltage spike on the collector of the igbt. without this, the igbt would see a heavy spike on the collector and hence resulting in a permanent damage to the device when it? turned off immediately. 5. under voltage lockout under voltage detection prevents the application of insufficient gate voltage to the igbt. this could be dan- gerous, as it would drive the igbt out of saturation and into the linear operation where the losses are very high and quickly overheated. this feature ensures the proper operating of the igbts. the output voltage, v o , remains low irregardless of the inputs as long as the supply volt- age, v dd2 ?v e , is less than v ulvo+ . when the supply voltage falls below v ulvo- , v o will go low, as illustrated in figure 54. 6. time to good power at initial power up, the led is off and the output of the gate driver should be in the low or off state. sometimes race conditions exist that causes the output to follow the v d (assuming v dd2 and v e are connected externally), until all of the circuits in the output ic have stabilized. this condition can result in output transitions or tran- sients that are coupled to the driven igbt. these transients can cause the high and low side igbts to conduct shoot-through current that may result in destruc- tive damage to the power semiconductor devices. fairchild has introduced an initial turn-on delay which is generally regarded as ?ime to good power? this delay, typically 30?, is only present during the initial power-up of the device. once powered, the ?ime to good power delay is determined by the delay of the uvlo circuitry. if the led is ?n?during the initial turn-on activation, low to high transition at the output of the gate driver will only occur 30? after the v dd2 power is applied. 7. dual supply operation ?negative bias at vss the igbt? off-state noise immunity can be enhanced by providing a negative gate to emitter bias when the igbt is in the off-state. this static off-state bias can be supplied by connecting a separate negative voltage source between the v e (pin 16) and v ss (pin 9 &10). figure 51 illustrates the two distinct grounds. the primary ground reference is the igbt? emitter connection - v e , pin 16. the under-voltage threshold and desaturation voltage detection are referenced to the igbt? emitter (v e ) ground. the recommended application circuit, figure 50, shows the interconnection of the v dd2 and v e supplies. the igbt? gate to emitter voltage is the absolute value sum of the v dd2 supply and the v ss reverse bias. the negative voltage supply at v ss appears at the gate drive input, v o , when the FOD8316 is in the low state. when www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 24 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing the input drives the output high, the output voltage, v o , will have the potential of the v dd2 and v ss . figure 50 shows the operation with a dual or split power supply. the vss supply provides the negative gate bias, and v dd2 + v ss supplies power to the output ic. the v ss and v dd2 supplies require three power supply bypass capacitors. these capacitors provide the low equivalent series resistant (esr) paths for the instantaneous gate charging and discharging currents. selecting capacitors with low esr will optimize the available output current. c3 is a low esr 1812 style, 10?, multilayer ceramic capacitor. this capacitor is the primary filter for the vss and v dd2 supplies. c1 and c2 are also low esr capacitors. they provide the primary gate charge and discharge paths. the schottky diode, d1, is connected between v e and v ss to protect against a reverse voltage greater than 0.5v. figure 52. input/output relationship figure 53. timing relationship among desatuation voltage (desat), fault output (f a ul t ) and fault reset input (reset ) v o v in? v in+ normal operation fault condition reset reset v o fault v desat v in? 0v 5v 7v 0v v in+ blanking time www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 25 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing figure 54. under voltage lockout (uvlo) for output side v o v dd2 ? v e 5v 0v v uvlo+ v uvlo? v in? v in+ www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 26 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing ordering information all packages are lead free per jedec: j-std-020b standard. marking information part number package packing method FOD8316 so 16-pin tube (50 units per tube) FOD8316r2 so 16-pin tape and reel (750 units per reel) FOD8316v so 16-pin, din en/iec 60747-5-5 option tube (50 units per tube) FOD8316r2v so 16-pin, din en/iec 60747-5-5 option tape and reel (750 units per reel) 1 2 8 4 3 5 de?itions 1 fairchild logo 2 device number, e.g., ?8316? for FOD8316 3 din en/iec60747-5-5 option (only appears on component ordered with this option) 4 plant code, e.g., ?d? 5 last digit year code, e.g., ?b? for 2011 6 two digit work week ranging from ?01? to ?53? 7 lot traceability code 8 package assembly code, j 8316 d x yy kk j v 6 7 www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 27 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing re?w pro?e pro?e freature pb-free assembly pro?e temperature min. (tsmin) 150c temperature max. (tsmax) 200c time (t s ) from (tsmin to tsmax) 60?120 seconds ramp-up rate (t l to t p ) 3c/second max. liquidous temperature (t l ) 217c time (t l ) maintained above (t l ) 60?150 seconds peak body package temperature 260c +0c / ?5c time (t p ) within 5c of 260c 30 seconds ramp-down rate (t p to t l ) 6c/second max. time 25c to peak temperature 8 minutes max. time (seconds) temperature (?) time 25? to peak 260 240 220 200 180 160 140 120 100 80 60 40 20 0 t l t s t l t p t p ts m a x ts m i n 120 preheat area max. ramp-up rate = 3?/s max. ramp-down rate = 6?/s 240 360 www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 28 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing package dimensions package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ 16 15 14 13 12 11 10 9 12345678 0.406 0.10 (10.312 0.254) 0.295 0.010 (7.493 0.254) recommended land pattern 0.018 (0.457) 0.025 (0.64) 0.138 0.005 (3.505 0.127) dimensions in inches (millimeters) 9 0.8 0.345 0.100 (8.763 0.254) 0.025 min. 0.050 (1.27) 0.050 (1.27) 0.008 0.003 (0.203 0.076) standoff all leads to be coplanar 0.002 0.408 0.010 (10.363 0.254) 0.085 (2.16) 0.458 (11.63) www.datasheet.net/ datasheet pdf - http://www..co.kr/
?010 fairchild semiconductor corporation www.fairchildsemi.com FOD8316 rev. 1.2.0 29 FOD8316 ?2.5a output current, igbt drive optocoupler with desaturation detection and isolated fault sensing www.datasheet.net/ datasheet pdf - http://www..co.kr/

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